5201-MNET-DNPSNET PROSOFT MODBUS TCP/IP到DNP 3.0以太網(wǎng)網(wǎng)關(guān)

5201-MNET-DNPSNET PROSOFT MODBUS TCP/IP到DNP 3.0以太網(wǎng)網(wǎng)關(guān)

第二(或許是最重要的)，就是實(shí)現(xiàn)系統(tǒng)的可靠性。要達(dá)到控制系統(tǒng)的絕對(duì)可靠性，SEARI試圖尋找同時(shí)支持硬件和軟件冗余的控制體系結(jié)構(gòu)。第三，就是確保控制的精確性，上海市政污水處理公司要求抽水站PLC和中央控制室的反饋時(shí)問(wèn)最好小于20毫秒。
最后，抽水站出現(xiàn)的腐蝕環(huán)境提出了進(jìn)一步的挑戰(zhàn)。硫化氫氣體是廢水中微生物自然分解的產(chǎn)物一反過(guò)來(lái)，硫化氫就會(huì)與氧發(fā)生反應(yīng)產(chǎn)生腐蝕性硫酸。

解決方案
在準(zhǔn)備第二階段的廢水處理系統(tǒng)升級(jí)方案時(shí)，SEARI找到了羅克韋爾自動(dòng)化上海公司。在亞太地區(qū)合作伙伴ProSoft技術(shù)的輔助下，羅克韋爾自動(dòng)化上海全球制造解決方案工程師展示了公司的Allen-Bradley PLC-5控制器通過(guò)集成一個(gè)專用的DNP通信模塊與DNP協(xié)議進(jìn)行通信的能力。
ProSoft的3800-DNP模塊設(shè)計(jì)可以直接安裝到Allen-Bradley PLC-5機(jī)架上，提供一種無(wú)縫集成基礎(chǔ)。同時(shí)，DNP-3800具有兩個(gè)通信端口，使得SEARI可以為每個(gè)抽水站安裝一個(gè)冗余的數(shù)據(jù)通信系統(tǒng)。
羅克韋爾自動(dòng)化抽水站控制解決方案包括兩個(gè)具有熱備份功能的獨(dú)立PLC-5，以便提供絕對(duì)的控制冗余。方案包括兩個(gè)位于獨(dú)立支架上的處理器，兩個(gè)處理器之間通過(guò)Allen一Bradley遠(yuǎn)程I/O(RIO)協(xié)議連接

ARCHITECTU
SW-QUARTUS-SE-ADD - ALTERA CORPORATION - QUARTUS II FLOATING NODE ADDITIONAL SEAT FOR ALL DEVICES ON WIN/LINUX, CORE ARCHITECTURE:CPLD, FPGA, SUPPORTED FAMILIES:CYCLONE, ARRIA, MAX, STRATIX
SW-QUARTUS-SE-FLT - ALTERA CORPORATION - QUARTUS II FLOATING NODE 1YR SUBSCRIPTION FOR ALL DEVICES ON WIN/LINUX, CORE ARCHITECTURE:CPLD, FPGA, SUPPORTED FAMILIES:QUARTUS II, NIOS II, SOFTWARE
ADD-FLOATALL - ALTERA CORPORATION - QUARTUS II SOFTWARE ADDITIONAL FLOATING-NODE SEAT, SUPPORTED FAMILIES:QUARTUS II, LICENSE TYPE:NETWORKED, SUPPORTED HOSTS:WINDOWS, LINUX, UNIX, SERIES
DK-DEV-3CLS200N - ALTERA CORPORATION - CYCLONE III LS FPGA DEVELOPMENT KIT, SILICON MANUFACTURER:ALTERA, CORE ARCHITECTURE:FPGA, CORE SUB-ARCHITECTURE:CYCLONE, SILICON CORE NUMBER:EP3C, SIL
DK-DSP-3SL150N - ALTERA CORPORATION - STRATIX III DSP DEVELOPMENT KIT, SILICON MANUFACTURER:ALTERA, CORE ARCHITECTURE:FPGA, CORE SUB-ARCHITECTURE:STRATIX, SILICON CORE NUMBER:EP3S, SILICON
DK-DEV-2AGX260N - ALTERA CORPORATION - ARRIA II GX FPGA DEVELOPMENT KIT, 6G EDITION, SILICON MANUFACTURER:ALTERA, CORE ARCHITECTURE:FPGA, CORE SUB-ARCHITECTURE:ARRIA, SILICON CORE NUMBER:EP
IP-FIR - ALTERA CORPORATION - IP CORE - FIR FILTER COMPILER, SOFTWARE APPLICATION:IP CORE, DSP FILTERS AND TRANSFORMS, CORE ARCHITECTURE:FPGA, CORE SUB-ARCHITECTURE:ARRIA, CYCLONE,
IP-FIRII - ALTERA CORPORATION - IP CORE - FIR FILTER COMPILER II, SOFTWARE APPLICATION:IP CORE, DSP FILTERS AND TRANSFORMS, CORE ARCHITECTURE:FPGA, CORE SUB-ARCHITECTURE:ARRIA, CYCLO
IPSR-BASE - ALTERA CORPORATION - IPS-BASE RENEWAL, SOFTWARE APPLICATION:IP CORE, SUITES, CORE ARCHITECTURE:FPGA, CORE SUB-ARCHITECTURE:STRATIX, SUPPORTED FAMILIES:STRATIX FPGA, FEATUR
IPT-C2H-NIOS - ALTERA CORPORATION - IP CORE - NIOS II C-TO-HARDWARE ACCELERATION COMPILER, SOFTWARE APPLICATION:IP CORE, NIOS PROCESSOR AND FUNCTIONS, CORE ARCHITECTURE:FPGA, CORE SUB-AR
DK-SI-4SGX230N - ALTERA CORPORATION - STRATIX IV GX TRANSCEIVER SIGNAL INTEGRITY DEVELOPM